1. Field of the Invention
The present invention relates to an integrated circuit chip and a method of manufacturing the same, and more particularly, to a structure at the edge of an integrated circuit chip and a method of forming the same.
2. Description of the Related Art
A plurality of integrated circuit chips are generally simultaneously formed on one wafer. The completed chips are sawed one by one and are packaged. Referring to FIG. 1 which is a plan view showing part of the surface of a wafer on which a plurality of integrated circuit chips are formed, chips 10 are formed on the wafer at predetermined intervals using the same process. The chips 10 are separated from each other by scribe lines 20 which define spaces for sawing the chips 10.
Referring to FIG. 2 which is an enlarged sectional view taken along the line 2—2 of FIG. 1, metal interconnections 40 and a contact 60 are formed in the chip 10. Interlayer dielectric films 30 are interposed between the metal interconnections 40. The uppermost part is covered with a passivation film 50. Also, since the area occupied by the scribe lines 20 is not generally used as a device, only interlayer dielectric films 30 and a passivation film 50 exist. However predetermined circuit patterns 45 referred to as a test element group (TEG) may be formed in order to estimate the characteristics of a device which is being designed in advance. Also, trenches 70 are formed at the boundaries of the chips 10 and the scribe lines 20. This is for cutting the passivation film 50, since mechanical shock generated when the chips are sawed along the center of the scribe line 20 and separated from each other is transmitted to the chip 10 through the passivation film 50 formed of silicon nitride, which is a hard material, The shock is strong if there is no trench 70, thus causing cracks to occur in the passivation film 50 and the device under the passivation film 50 of the chip 10. The trench 70 is formed in an etching process also used to form a fuse opening (not shown) of the chip 10 without in order to reduce the number of processes. The wafer is sawed along the center of the scribe line 20 and divided into separate chips. In FIG, 2, the part between dotted lines 80 is sawed and removed. The entire width of the scribe line 20 is generally between about 100 and 120 μm. The width of the sawed and removed part (the part between dotted lines 80) is generally between about 30 and 60 μm.
In general, before the completed chips 10 are sawed, the reliability of the wafer shown in FIG. 2 is tested at a temperature of between 100 and 150° C., a humidity of between 80 and 100%, and a pressure of between 1.5 and 3 atm, in order to estimate whether the completed integrated circuit chips operate in a stable condition at a high temperature, a high humidity, and a high pressure.
The interlayer dielectric films 30 exposed on the sidewalls of the trenches 70 located at the edges of the chips 10 are usually formed of silicon oxide such as boron phosphorous silicate glass (BPSG), phosphorous silicate glass (PSG), spin on glass (SOG), tetra ethyl ortho silicate (TEOS), and undoped silicate glass (USG), which have an excellent planarization characteristic. However, the BPSG, the PSG, the SOG, and the TEOS, which include a high concentration of impurities such as boron greater than or equal to 5 weight % and phosphorous greater than or equal to 4 weight %, are vulnerable to moisture. Furthermore, in order to prevent changes in the characteristics of the device, the interlayer dielectric films 30 are formed at a low temperature. Therefore, when moisture seeps into interfaces between the interlayer dielectric films 30 vulnerable to moisture while test the reliability of the device, the metal interconnections 40 formed of tungsten or aluminum and the contact 60 in an adjacent peripheral circuit erode and the interfaces between the interlayer dielectric films 30 or the interfaces between the interlayer dielectric films 30 and the metal interconnections 40 are peeled from each other, or cracks occur in the interfaces between the interlayer dielectric films 30 or the interfaces between the interlayer dielectric films 30 and the metal interconnections 40. Accordingly, the reliability of the device severely deteriorates.
Similar problems occur in the fuse opening (not shown) in the chip 10. In order to solve the problems in the fuse opening, a method of forming an anti-moisture-absorption film with a moisture-proof material on the sidewall of the fuse opening (U.S. Pat. No. 5,879,966) and a method of forming a ring-shaped guard ring which surrounds the fuse opening (Japanese Patent Publication No. Hei 9-69571) are provided. However, when using these methods, it is necessary to add process steps. Also, such methods have not been provided with respect to the edges of the chips.